1. Field of the Invention
The present invention generally relates to a semiconductor package and a method of manufacturing the same. More particularly, the present invention relates to a package that may reduce flash contamination and a method of manufacturing the same.
2. Description of the Related Art
Semiconductor packages may be used to house semiconductor chips. It is generally desirable for such packages to be scaled down in size due to a reduction in the size of electronic devices. To this end, conventional semiconductor packages that employ leads as external connection terminals, such as (for example) a small outline package (SOP), a plastic leaded chip carrier (PLCC), a plastic quad flat package (PQFP) and a pin grid array (PGA), may have been superseded by new semiconductor packages that employ solder balls or solder bumps as external connection terminals, such as (for example) a ball grid array (BGA) and a chip scale package (CSP). External connection terminals in the form of leads may be replaced by external connection terminals in the form of solder balls because the use of solder balls may provide for decreases in the sizes of semiconductor packages.
For semiconductor packages using solder balls as external connection terminals, solder joint reliability (SJR) is a consideration.
FIG. 1 is a cross-sectional view of a conventional wire-bonding BGA package.
Referring to FIG. 1, wire bonding may be performed near the center of a BGA substrate 10. An epoxy mold compound (EMC) may be applied via a molding process onto a bond wire 70 and a portion of a semiconductor chip 30 exposed via the substrate 10. The resultant structure may be referred to as a wire bonding BGA (WBBGA) package 90.
In the WBBGA package 90, the substrate 10 may include a substrate body 12, a copper pattern 14 and a solder resist 16. The substrate body 12 may be formed of an insulating material, such as a glass fiber epoxy laminate (e.g., FR4). The copper pattern 14 may be formed on the substrate body 12 and may include a ball land. The solder resist 16 may be coated on the copper pattern 14 to protect the copper pattern 14 from a short. A solder ball 20, which serves as an external connection terminal, may be attached to a surface of the substrate 10. A first EMC portion 50B may be molded to encapsulate the bond wire 70. The first EMC portion 50B may be located at the center of the substrate 10. A semiconductor chip 30 may be mounted on a surface of the substrate 10 opposed to the surface on which the solder ball 20 is attached. The semiconductor chip 30 may be mounted on the substrate 10 using an adhesive 40. A second EMC portion 50A may be molded to encapsulate the semiconductor chip 30 and the adhesive 40.
However, when the WBBGA package 90 is manufactured, flash contamination may occur during a molding process for forming the first EMC portion 50B. Such flash contamination may weaken the adhesion strength of the solder ball 20 to the WBBGA package 90.
FIG. 2 is a partial magnified plan view of the WBBGA package 90 depicted in FIG. 1 when the flash contamination occurs. In FIG. 2, the solder balls 20 are not depicted for clarity.
Referring to FIG. 2, a flash 60 may be generated when the first EMC portion 50B is formed via a molding process. The term flash refers to remnants of the EMC that may flow away from the first EMC portion 50B (and onto unintended portions of the substrate 10) during the formation of the first EMC portion 50B. Generally, the EMC should be formed without generating flash defects. However, flash defects may be inevitable due to the flatness of the substrate 10 (see FIG. 1), the performance of a molding apparatus, and the like. When flash 60 is generated, the EMC may flow in an unobstructed fashion over the solder resist 16 on the substrate body 12 and may contaminate a ball land 14A of the copper pattern 14. The contamination caused by the flash 60 may weaken the adhesion strength of the solder ball 20 (see FIG. 1) to the ball land 14A during a process of attaching the solder ball 20 to the ball land 14A, thus lowering the SJR.
FIG. 3 is a cross-sectional view taken along line III–III′ of FIG. 2, and FIG. 4 is a cross-sectional view of a portion IV of FIG. 2 in which flash contamination has occurred.
Referring to FIGS. 3 and 4, in a substrate for a BGA package, a copper pattern including the ball land 14A may be formed on a substrate body 12, and a solder resist 16 may be formed on the copper pattern. Thus, a portion of the substrate where the solder resist 16 is formed may have a high height, as compared to the heights other portions of the substrate where the solder resist 16 is not formed, e.g. the ball lands 14A. Hence, if a flash is generated, the flash may naturally flow from the solder resist 16 along the substrate body 12 an onto the ball land 14A.